Etienne Borde is an assistant professor and researcher at Telecom ParisTech where he focuses on software engineering for real-time embedded systems. His research interests include component-based software engineering, architecture description languages, model transformation, code generation, and formal verification. In this research, he applies and develops techniques to improve design methods of real-time embedded systems.
Peter Feiler is the technical lead and author of the Architecture Analysis & Design Language (AADL) Standard. For the last 25 years, Feiler has been a senior member of the technical staff at the SEI where his research areas include dependable real-time systems, architecture languages for embedded systems, and predictable system analysis and engineering. In 2009, he received the Carnegie Science Award for Information Technology for his work with AADL.
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