Using All Processor Cores While Being Confident about Timing
October 2019 • Presentation
This presentation describes research to address the use of all processor cores while retaining confidence about timing.
Software Engineering Institute
In this project, we aim to develop a solution to overcome this obstacle. This is a difficult challenge, because timing is determined by many shared resources in the memory system (including cache, memory banks, memory bus) with complex arbitration mechanisms, some of which are undocumented. The goal of our research is to demonstrate multicore timing confidence.