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Final Evaluation of MIPS M/500 Final Report for the RISC Insertion Project

November 1987 Technical Report
Dan Klein, Robert Firth

This 1987 report describes the evaluation of the MIPS M/500 RISC processor1 as part of ongoing research into RISC class architectures.

Publisher:

Software Engineering Institute

CMU/SEI Report Number

CMU/SEI-87-TR-025

Abstract

In response to a request from the DoD, an analysis of a Reduced Instruction Set Computer (RISC) processor, the MIPS M/500, was performed. All aspects of processor capabilities and support software were evaluated, tested, and compared to familiar Complex Instruction Set Computer (CISC) architectures. In all cases, the RISC computer and its support software performed better than a comparable CISC computer. This report provides the general and specific results of these analyses, along with the recommendation that the DoD and other government agencies seriously consider this or other RISC architectures as a highly viable and attractive alternative to the more familiar but less efficient CISC architectures.