Software Engineering Institute

In this work, researchers propose to build a benchmark baseline based on commercial off-the-shelf (COTS) field-programmable gate array (FPGA) hardware and compete in the DARPA Graph Challenge to demonstrate the FPGA’s power and performance advantages for the graph problems targeted by this program. If successful, the graph primitives identified for FPGA could be transitioned to lower power ASIC designs and could inform chip designers by more concretely defining the measures of success for the new graph processing chip.